The present invention relates to an electrically programmable non-volatile memory and to an integrated circuit comprising a memory of this kind. More specifically, the present invention relates to a non-volatile memory using field avalanche metal oxide semiconductor (FAMOS) technology, which uses a natural memory cell obtained with a P-type MOS transistor whose single gate is electrically insulated.
A natural memory cell is obtained without adding complementary steps to the basic process for the manufacture of a P-type MOS transistor. In particular, it has only one polysilicon level unlike the other types of known memories, for example, EPROM or EEPROM type memory cells. Since the gate of an FAMOS transistor is not connected, it is not possible to electrically erase an FAMOS memory cell. For this reason, ultraviolet rays have to be used. A memory cell of this kind is therefore used more particularly as a one-time programmable (OTP) memory.
An FAMOS type memory cell can be distinguished simply from a classic P-type transistor by the fact that its single gate is not electrically connected. An FAMOS memory cell is programmed, for example, by applying a programming voltage VPP of about 5 V to its source for about 500 xcexcs, with its drain being connected to ground. The gate potential then rises by capacitive coupling between, first, the gate and, second, the source and the well. Hot electrons are created at the drain and these electrons are injected into the gate.
In the blank state (or the state when it is erased by UV rays), the FAMOS memory cell has a threshold voltage VT1 of about xe2x88x920.6 V. When it is programmed, its threshold voltage VT2 reaches about 1 V.
A memory cell is read by measuring the current flowing between its source and its drain when a voltage ranging from a few hundred millivolts to a few volts is applied between its source and its drain. For example, a read voltage of about 3.3 V is applied to its source and a power supply voltage of about 2.3 V is applied to its drain. Read and write access to the memory cell is obtained in a known way by an access transistor series-connected with a memory cell.
To make a memory, several memory cells are used. These memory cells are associated in a memory array comprising a set of rows and a set of columns. Each row forms a word of several bits. All the memory cells of the same word are connected together to the same word line, and all the memory cells of the same column are connected together to the same bit line. It is possible to select each memory cell by choosing a word line and a bit line. French Patent No. FR 10286 describes an exemplary embodiment of an FAMOS memory.
One problem that arises when making a memory is that of insulating the memory cells from one another. Another problem is the speed of programming or reading a memory cell. This speed is limited by the size of the access transistor associated with the memory cell to be programmed or read.
There are known ways of using a field oxide zone or region to insulate two active elements of an integrated circuit. The field oxide region may be deposited by several methods, such as the LOCOS (local oxidation) method or the STI (shallow trench insulation) method.
The STI method is advantageous because it can be used to obtain thin field oxides. However, this method creates brittle regions, more commonly known as birds"" beaks, at the interface between the gate and insulator. This method also raises risks of the dislocation of the silicon at the interface between the field oxide and the active region.
The brittle regions or regions of dislocation essentially reduce the time during which data is held in the FAMOS transistor. Furthermore, regardless of the method used, the depositing of a field oxide requires an additional step in the general method of manufacture of the memory.
Details on insulation by field oxide deposition, its advantages and its drawbacks as well as information on what is called the bird""s beak phenomenon are specified in the French Patent No. FR 10287. To resolve the problem of the time during which data is held in the FAMOS transistor, the French Patent No. FR 10287 discloses the use of a memory cell having a ring structure, i.e., the active elements of the memory cell are made in concentric forms.
Such a structure has the advantage of not using field oxide to separate the active elements of the FAMOS transistor. There are therefore no bird""s beak type phenomena with such a structure. This approach is useful for making a FAMOS memory cell but cannot be used for making a memory. Indeed, it is hard to make a set of concentric memory cells, especially if there are a large number of memory cells to be made.
In view of the foregoing background, an object of the present invention is to insulate the memory cells of a FAMOS memory without using the field oxide, so as not to create regions of brittleness that could give rise to the dislocation phenomena.
Another object of the present invention is to increase the speed of programming or reading a memory cell of the memory.
Yet another object of the present invention is to provide a memory structure such that it has no regions of brittleness that could give rise to a bird""s beak type of phenomenon.
These and other objects, advantages and features according to the present invention are provided by a FAMOS memory comprising at least one first cell and one second cell, with the first and second cells each comprising a transistor whose single gate is insulated. A first access transistor having a diffusion region is connected to a diffusion region of the insulated gate transistor.
The memory also comprises an insulation transistor for which a diffusion region is connected, first, to the diffusion region of the insulated gate transistor of the first cell and, second, to the diffusion region of the insulated gate transistor of the second cell. It will be recalled that the ends of a diffusion region form the drain and the source of a transistor.
Thus, a memory according to the invention comprises an insulation transistor placed between two memory cells of the same row of the memory. A memory according to the invention therefore does not include any insulator in the form of a field oxide. The risk of the dislocation phenomena appearing, and hence the risk of a reduction in the time during which data is held in the memory are thus eliminated.
Furthermore, connecting the gate of the insulated transistor and the gates of the access transistor of the first cell and of the second cell makes the insulation transistor become conductive at the same time as the access transistors. When it is on, the insulation transistor is equivalent to a wire and all the access transistors of the first cell and of the second cell are parallel connected and their effects are added together, i.e., they become equivalent to a single access transistor with a far greater size (in terms of gate width/length ratio). The consequence of this is that the speed of access to the insulated gate transistor of one of the cells is increased. The duration of a programming operation or read operation in this transistor is therefore reduced accordingly, and the programming or reading quality is thereby improved.
The invention preferably uses only one type of transistor, in this case, P-type transistors. The making of the memory is thus facilitated. According to one embodiment of the invention, the first cell and/or the second cell also each comprise a second access transistor, having a gate, a source and a drain respectively connected to a gate, a source and a drain of the first access transistor.
In a same cell, the first access transistor and the second access transistor are parallel connected, and their effects are added together. Consequently, the speed of access to the associated isolated gate transistor is further increased.
In the first cell and/or in the second cell a drain of the insulated gate transistor is connected to an associated bit line, and the gate of the access transistors are connected to an associated word line. The source of the access transistors are connected to a power supply line, and the drain of the access transistors are connected to the source of the insulated gate transistor. Thus, by applying appropriate voltages to the power supply line, on a bit line and on a word line, it is possible to read or program an associated insulated gate transistor.
Preferably, the insulation transistor and the access transistors for all the cells have a common gate. In this case, all these transistors may be controlled together. Preferably, the insulated gate transistor of the first cell or the second cell has a ring structure comprising a central diffusion region, a peripheral diffusion region and a polysilicon region located between the central diffusion region and the peripheral diffusion region.
A memory according to the invention thus derives all the advantages related to the ring structure of an FAMOS transistor. For example, the invention eliminates the risk of creation of brittle regions and further increases the data holding time.
Furthermore, due to its ring structure, the surface of the drain of the insulated gate transistor, and hence the junction area of this drain with the associated bit line is reduced. The junction capacity of such a transistor is thus about three times smaller than the junction capacity of a linear transistor having the same W/L size (in terms of the gate width/length ratio).
It is possible to choose an insulated gate transistor with a large W/L ratio inasmuch as its junction capacity is smaller than that of an equivalent linear transistor. The reading time of the transistor is thus reduced and the quality of the reading is improved. Another advantage of the ring structure is that it reduces the leakage currents.
More generally, a memory according to the invention comprises M*N insulated gate transistors in a ring structure, distributed in N rows of M columns. The insulated gate transistors comprise a central diffusion region forming a drain and a peripheral diffusion region forming a source. All the insulated gate transistors of the same column have their drain connected together to the same bit line.
For each row, a separation region separates the M insulated gate transistors of the row. For each row, the separation region has a ladder shape and comprises a first upright located substantially parallel to an axis of the M insulated gate transistors and bordering the peripheral diffusion region of the M insulated gate transistors. Each row also comprises a second upright symmetrical with the first upright, with respect to the axis of the M insulated gate transistors. Mxe2x88x921 rungs or steps are perpendicular to the first upright and the second upright, with each step being located between two adjacent insulated gate transistors and between the first upright and the second upright.
The peripheral diffusion region of the m ranking insulated gate transistor, with m being an integer ranging from 1 to Mxe2x88x921, the m ranking step, and the peripheral diffusion region of the m+1 ranking insulated gate transistor form an insulation transistor.
Similarly, the separation region of the n ranking row and the separation region of the n+1 ranking row, with n being an integer ranging from 1 to Nxe2x88x921, have a same contact line in common. This contact line is located between the second upright of the separation region of the n ranking row and the first upright of the separation region of the n+1 ranking row.
The peripheral diffusion region of the mth insulated gate transistor of the nth row, the second upright of the separation region of the n ranking row and a diffusion region connected to the contact line by a contact point respectively form the drain, the gate and the source of an access transistor associated with the mth insulated gate transistor of the nth row.
Symmetrically, the diffusion region connected to the contact line by the contact point, the first upright of the separation region of the n+1 ranking row and the peripheral diffusion region of the mth insulated gate transistor of the (n+1)th row, respectively form the drain, the gate and the source of an access transistor associated with the mth insulated gate transistor of the (n+1)th row.